TRL & Hardware Development Phases - Mapping Technology Readiness Levels to Concept / EVT / DVT / PVT / Mass Production

TRL (Technology Readiness Level according NASA definition and as used in EU) is a scale from 1 to 9 that measures the maturity of a technology independent of its production readiness. The hardware development gate framework (Concept → EVT → DVT → PVT → Mass Production) measures the combined readiness of technology, design, manufacturing process, supply chain and quality system.

The two frameworks are complementary, not redundant. A product can enter EVT with a high-TRL core technology (e.g. a known battery chemistry at TRL 6) while a subsystem such as firmware integration may still be at TRL 3. The gate framework governs the whole product — which is why each discipline (Mechanical, Electrical, Firmware, Supply Chain, Hardware Operations, Quality, etc.) has its own exit criteria per gate rather than a single TRL number for the system.

Often, internal conversations mix up the discussion of Technical Readiness Level (e.g. used in Research heavy environments) and the Hardware Phase Gates, much more known in product development heavy environments.

TRL-to-Phase Mapping

The table below maps each TRL level to the corresponding hardware development phase and key activities. Coloured cells indicate where a TRL is primarily achieved; empty cells indicate the phase is not the primary driver for that TRL.

When talking about the Hardware Phase-Gates, always remember those have exit criteria for all relevant disciplines of engineering and operation. There are some common misunderstandings when using the frameworks.

TRL is technology-centric; EVT/DVT/PVT is product and manufacturing-centric.

Several nuances are important:

• A product can enter EVT at TRL 4 with a high-TRL core technology. TRL is always assessed at subsystem level; the gate assessment is product-level.
• TRL 6 and TRL 7 both map to DVT because DVT spans from first system-level integration (TRL 6) through operational demonstration including the pilot run (TRL 7).
• TRL 8 is only achievable when manufacturing qualification is complete — a product with all engineering tests passed but no production yield data has not reached TRL 8.
• TRL 9 cannot be declared at gate. It requires field evidence accrued post-Ready-to-Ship, typically 3–6 months after mass production start.
• Do not use TRL as a substitute for gate discipline. A team can claim TRL 6 after a single demo unit; the DVT gate may require 10–20 units, analysed yield data, and cross-functional sign-off. When developing a hardware product, use TRL for the engineering team but the cross-functional product/engineering/operations team should work toward the hardware phase gates and maintain gate discipline to avoid failure and blind spots watering down and becoming more painful and expensive with every phase passed.

The table below gives a high-level idea of TRL achievements mapped into the hardware development framework.

Each phase gate corresponds to a minimum TRL threshold. Passing a gate does not guarantee TRL is fully achieved — it means the evidence base is sufficient to proceed to the next phase under defined risk acceptance. Each Phase Gate always always observes the full spectrum of stakeholders including engineering, product definition, certification, supply chain, operation (incl. maintenance) etc.

Phase-by-Phase Narrative with Key activities

TRL 1–3 → Kickoff Concept / Pre-EVT

This is the research and feasibility zone. Key activities include:

• PRD Part 1 (problem statement) and Part 2 (Product Definition) incl. business case, target markets, lifetime volume defined
• Stakeholders identified
• Resources identified
• PoC work and feasibility assessments
• Make or Buy decisions taken (Design & Build or Spec & Buy)

No hardware gates apply yet. The team establishes that the physics works and that a buildable product concept exists which corresponds to the first set of product requirements from the problem statement. The Ready to Design Gate closes this phase.

TRL 4–5 → EVT (Engineering Validation Test)

The technology moves from the lab bench to a controlled prototype environment. TRL 4 covers breadboard-level component validation; TRL 5 is the full EVT phase where Prototype builds validate the design in a realistic environment. Key deliverables include:

• Functional testing of all product features against the PRD, UX review
• Engineering Requirement Testing e.g. Thermal / Structural analysis
• First DFM review and sign-off
• BOM 80% complete with long-lead parts identified and PO placed
• Supply Chain Issues identified and in mitigation
• Certification strategy defined
• Product Feature list is locked
• Software MVP ready

The Ready to Validate gate marks the exit. Engineering team confidence on TRL5 is a formal gate input.

TRL 6–7 → DVT (Design Validation Test)

The system becomes a representative prototype tested in operational conditions. TRL 6 corresponds to DVT builds validating the full system against spec including reliability, EMC and environmental performance. TRL 7 is reached when the prototype is demonstrated credibly in the target operational environment — including a pilot production run (number of units depends on the product) that proves the manufacturing process, not just the design. Key deliverables:

• DVT Builds ready, assembly procedure verified
• Pilot run yield ≥90%; passed analysis of all defect modes
• High-risk reliability tests (e.g. EMI, environmental) complete or in-progress
• Certification pre-testing with notified body (no blockers)
• Operational numbers for assembly, maintenance and repair are defined and tested
• All suppliers confirmed for volume; BOM cost in supply chain control, Spare Parts defined and pre-ordered
• Quality Control Measures in place internally and with suppliers & manufacturers
• Design freeze in effect post-DVT; all further changes require formal change approval + sign-off

The Ready to Ramp Up gate marks the exit to mass production.

TRL 8 → PVT (Production Validation Test)

The system is complete and qualified. The design freeze is in full effect. Key deliverables:

• PVT hardware builds (first set of true mass units)
• First-pass yield ≥95% (production-ready target)
• All certifications obtained (CE, FCC, RoHS, UL, etc.)
• Firmware Gold Master locked and production image deployed
• Supply chain confirmed ready for volume ramp; POs placed
• EFFA (Early Field Failure Analysis) plan active from production start
• Team lined up for daily operation on mass level
• Software Features implemented, Firmware locked
• Launch Plan confirmed, Marketing Plan confirmed

Passing the Ready to Ship / Mass Production Gate includes handoff documentation package is archived and locked for repeatable manufacturing.

TRL 9 → Mass Production / Field

The product is proven in the actual operational environment with real customers. TRL 9 is not a gate, it is earned through sustained field performance. Key activities:

• EFFA monitoring: target <1% field return rate in first 3 months
• Ongoing Reliability Testing) at the manufacturing side
• Field quality reviews with manufacturing and design teams
• Corrective action plan triggered if return rate exceeds target
• Continuous Improvement in place
• Cost-Down initiatives in place
• Spare Parts under control

The Team is Key - Psychological Safety Matters

The above framework can easily get adapted to every hardware product. The main factor for success still remains the team and the leadership within. Psychological Safety in the working environment guarantees honest gate reviews, holictis risk judgment and decision-making with discipline. A framework can give guidance but using it successfully is deeply depending on the team work. Read more here: Psychological Safety: The Hidden Cost of Teams That Stay Silent

If you are a founder or leader and sense that your teams are quiet when they should be speaking up, reach out or book a short call on Calendly to discuss your situation and see whether we are a fit.